FIG. 1 schematically shows a conventional device for synchronizing a reference event of an analog signal. Generally, the device is further provided to convert the synchronized analog signal into a digital signal.
A programmable delay line 1 receives an analog signal DLI1, and provides a delayed analog signal DLO1 to an analog-to-digital converter 3. Analog-to-digital converter 3 provides digital samples D1 at the rate of a clock signal CK0 generated by a phase-locked loop 5. A programmable delay line 2 receives an analog signal DLI2 and provides a delayed analog signal DLO2 to an analog-to-digital converter 4. Analog-to-digital converter 4 provides digital samples D2 at the rate of clock signal CK0. Delay lines 1 and 2 are respectively programmed by control signals COM(.DELTA.) and COM(.DELTA.') generated by a control signal 7 according to signals DLI1 and DLI2.
In an example, the reference event is a zero crossing of the signal. Control circuit 7 is then provided to set delay lines 1 and 2 so that the zero crossing of signal DLI1 is synchronized on the zero crossing of signal DLI2.
FIGS. 2A to 2D illustrate the operation of the device of FIG. 1. FIG. 2A shows a periodic analog signal DLI that transits through 0 at a time t0' advanced by a duration A with respect to a reference time t0.
FIG. 2B shows signal DLI2. Signal DLI2 transits through zero at time t0 delayed by a duration a with respect to reference time t0.
FIG. 2C shows clock signal CK0 generated by phase-locked loop 5. Reference time to is arbitrarily determined by a rising edge of clock signal CK0.
FIG. 2D shows two sequences of digital values ANO1 and AN02 sampled at the respective rising edges of signal CK0.
Control circuit 7 varies delays .DELTA. and .DELTA. introduced by the delay lines between signals DLO1 and DLO2 until the delay between the 0 crossing of signal DLO1 and of signal DLO2 is zero, or the smallest possible, according to what is enabled by the pitch of the delay line.
Although a circuit such as that in FIG. 1 operates satisfactorily, it has significant disadvantages. In particular, a digital circuit including a programmable analog delay line can only be formed in a BICMOS technology, which is expensive.
The features of a delay line, and especially its pitch, can considerably change if the manufacturing process changes. These feature variations are not desirable.
Further, an analog delay line is a delicate element, any modification of which must be performed with the utmost care. This element is said to be uneasily portable from one integrated circuit manufacturing technology to another.
Finally, current techniques do not enable obtaining programmable delay lines having a pitch smaller than an order of one nanosecond.